1. Field of the Invention
Embodiments of the invention relates to a non-volatile semiconductor memory device. In particular, embodiments of the invention relate to a high voltage transfer circuit, a row decoder circuit comprising the high voltage transfer circuit, and a non-volatile semiconductor memory device comprising the high voltage transfer circuit.
This application claims priority to Korean Patent Application 2006-45276, filed on May 19, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A semiconductor memory device may be generally classified as a volatile semiconductor memory device or a non-volatile semiconductor memory device. Dynamic random access memory (DRAM) and a static random access memory (SRAM) are types of volatile semiconductor memory. While volatile semiconductor memory devices have the benefit of relatively fast read and write speeds, they have the disadvantage of losing the data stored in memory cells when power is not supplied to the device.
Mask read only memory (MROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and the like are types of non-volatile semiconductor memory. Data stored in memory cells of a non-volatile semiconductor memory device can be retained even when power is not supplied to the device, so non-volatile semiconductor memory devices are mainly used to store data that must be retained regardless of whether power is being supplied. Users cannot readily erase MROM, PROM, or EPROM using just the electronic system in which a device of one of those types is disposed. However, an EEPROM device may be erased and written to electrically using the electronic system in which the device is disposed. Thus, the application of EEPROM has widened to auxiliary storage units or system program storage units in need of continuous updating.
Flash memory is a type of EEPROM, and a flash memory device performs a program operation using a hot electron injection mechanism in which electrons are injected to a floating gate of the memory cell from a channel region adjacent to a drain region of the memory cell. A memory cell is programmed by grounding source and substrate regions of the memory cell and applying a high voltage of about 9V to a control gate of the memory cell. At this time, the drain region is supplied with a voltage of about 5V, which is appropriate to generate hot electrons. As a result of the program operation, negative electrons are accumulated on the floating gate, thus increasing a threshold voltage of the memory cell. During an erase operation, a negative voltage of about −9V is applied to the control gate and a voltage of about 9V is applied to a bulk region of the memory cell. In accordance with this bias condition, negative electrons accumulated on the floating gate are discharged to the bulk region, which lowers the threshold voltage of the memory cell. A read operation is performed by applying a voltage of about 1V to the drain region, a voltage lower than a threshold voltage of the programmed memory cell to the control gate, and 0V to the source. If the memory cell on which the read operation is performed is programmed, then the memory cell is determined to be an “off-cell,” and if the memory cell is erased, then the memory cell is determined to be an “on-cell”. During a read operation, a voltage having a level that is between the threshold voltage of a programmed memory cell and the threshold voltage of an erased memory cell (which may be referred to hereinafter as a read voltage) is applied to a word line connected to a selected memory cell.
In addition, a flash memory device uses a boosted voltage that is higher than a power supply voltage. A row decoder circuit of the flash memory device is a circuit of the flash memory device that needs the boosted voltage. As is well known in the art, a flash memory device uses a relatively high voltage (i.e., a boosted voltage) of about 23V in order to perform program and erase operations. In addition, a high voltage switch is used to control the boosted voltage (i.e., the high voltage).
Figures (FIGS.) 1 to 3 are circuit diagrams illustrating conventional high voltage transfer circuits.
Referring to FIG. 1, a high voltage transfer circuit consists of a high-voltage PMOS transistor HV-PMOS acting as a switch and a level shifter. In general, the high-voltage PMOS transistor HV-PMOS has a low breakdown voltage between a drain and a source. For this reason, when the high-voltage PMOS transistor HV-PMOS is turned OFF and a relatively low voltage such as 0V is applied to an output node OUT, a voltage difference between the source and the drain of the high-voltage PMOS transistor HV-PMOS becomes large, which may cause a breakdown to occur (i.e., may cause a breakdown phenomenon).
FIG. 2 also illustrates a high voltage transfer circuit. The high voltage transfer circuit illustrated in FIG. 2 is substantially the same as the high voltage transfer circuit illustrated in FIG. 1, except that a high-voltage NMOS transistor HV-NMOS is used instead of the high-voltage PMOS transistor HV-PMOS of FIG. 1. As is well known in the art, high-voltage NMOS transistor HV-NMOS has a high breakdown voltage, so it is free from the breakdown phenomenon that may occur in the high voltage transfer circuit illustrated in FIG. 1. However, in order to transfer a boosted voltage VPP (i.e., a boosted voltage VPP) to output node OUT when the high-voltage NMOS transistor HV-NMOS is turned ON, a DC bias voltage greater than a voltage of (VPP+Vth) must be applied to a gate of high-voltage NMOS transistor HV-NMOS. In general, it is difficult to generate a voltage as high as boosted voltage VPP used in the flash memory device. Thus, generation of a voltage (i.e., the DC bias voltage) higher than boosted voltage VPP may cause various problems such as increase in current consumption, increase in chip size, and the like.
Another conventional high voltage transfer circuit, which is illustrated in FIG. 3, comprises a depletion-type transistor connected between boosted voltage VPP and a high-voltage PMOS transistor HV-PMOS. Boosted voltage VPP or a voltage of 0V is applied to a gate of the depletion-type transistor. In accordance with this configuration, it is possible to solve the breakdown phenomenon described above by preventing boosted voltage VPP from being applied to high-voltage PMOS transistor HV-PMOS when high-voltage PMOS transistor HV-PMOS is turned OFF (i.e., during a switch-off state). However, when a high voltage is applied to output node OUT, a breakdown phenomenon may occur when high-voltage PMOS transistor HV-PMOS is turned OFF (i.e., when high-voltage PMOS transistor HV-PMOS is in a switch-off state). Further, when a power supply voltage is lower than a threshold voltage Vthd of the depletion-type transistor during a low voltage operation in which an operating voltage lower than a conventional power supply voltage is used, leakage current may be generated when high-voltage PMOS transistor HV-PMOS is turned OFF. In order to prevent the leakage current from being generated, the high voltage transfer circuit requires a DC bias voltage Vbias received from outside of the high voltage transfer circuit, as illustrated in FIG. 3.